Open Source RFID Sensor Tag Verilog Code

Questions? - yeagerd yeagerd maintains this page.

Intro

We open-sourced the tag verilog state machine. We hope this will enable the community to move forward in developing more advanced RFID sensor tags without constantly reinventing the wheel (tag state machine).

Status

The code has been synthesized, fabricated, and tested in IBM130nm. The communication code works well, but feature requests, performance issues, and bugs are documented at the end of this page.

Additionally, this code can run on an Altera DE2 FPGA dev board (and others, I'm sure). This is particularly useful if you attach a WISP analog front end (AFE) to the FPGA dev board, and then you can do in situ testing with a live commercial reader over the air interface (not simulation). This helps iron out unexpected corner cases, such as partial packets, invalid packet sequences, etc. See below "Testing on an FPGA + Commercial Reader + WISP" for more details.

Features

  • Full EPC Gen2 support across Tari, Miller/FM0 backscatter encoding, etc. (not selective support, like WISP).
  • Supports a wide range of input clock frequencies (about 2 MHz up to 10 MHz). See Journal paper.
  • Has ADC and MSP430 interfaces
  • Modular, easily extensible

Architecture





Details

A 9uA, Addressable Gen2 Sensor Tag for Biosignal Acquisition, D. Yeager, F. Zhang, A. Zarrasvand, N. T. George, T. Daniel, B. P. Otis, IEEE Journal of Solid-State Circuits (JSSC), Vol. 45, No. 10, 2010. Daniel Yeager, "Development and Application of Wirelessly Powered Sensor Nodes" M.S. E.E., University of Washington, 2009.

Code

The code lives here: http://github.com/wisp/rfid-verilog. For general info on using the repository, visit Getting firmware and software.

Please cite: A 9uA, Addressable Gen2 Sensor Tag for Biosignal Acquisition, D. Yeager, F. Zhang, A. Zarrasvand, N. T. George, T. Daniel, B. P. Otis, IEEE Journal of Solid-State Circuits (JSSC), Vol. 45, No. 10, 2010. IEEE Xplore Abstract

To encourage community participation, you must download the code from GitHub. Please, please let us know if there is some impediment to you contributing back to the project!

Version Info (Main Releases)

Version
Date
Changes
Bugs
Notes
1.0
2010-10-21
None
FIFO Synthesis Failed
Initial version checked into git











Testing in Simulation

A tester is also checked into the git repository. Its not a proper RFID reader which would include DSP for recovering the backscatter from noisy ADC data. It is just a digital tester to verify the functionality of the tag logic. It is not complete; please pick up the testing if you feel compelled. However, the in situ test described in the next section is much easier and produces a more robust solution. Nevertheless, basic simulation-based testing is useful for initial development and for step-through debugging.

Testing on an FPGA + Commercial Reader + WISP

See the last chapter or two:
Daniel Yeager, "Development and Application of Wirelessly Powered Sensor Nodes" M.S. E.E., University of Washington, 2009.
Post on the discussion board if you have questions.

Bugs

  • The synthesized FIFO didn't work on the IBM / Cadence design flow. The DE2 synthesized it into SRAM or something, which implements differently. We believe that the use of addressed wires [0:15] got mangled (which is a known issue in some Cadence flows). User beware!

Requested Features

  • The two versions checked into git are nearly identical (the major difference is the FIFO buffer between the ADC and the Comm Logic). An IFDEF should be used to select which version to compiler so that the common code is shared.

Performance Issues

  • Current implementation is a bit power intensive (roughly 5uW at 500mV @ 500 reads/sec). There's not a fundamental reason for this, other than tapeout time constraints. Idle power is quite high; additional clock gating would benefit power consumption!





The last modification was made by - yeagerd yeagerd on Oct 27, 2010 9:28 pm